A New Architecture Design Implementation of Non- Redundant Radix-4 Signed Multiplier Using HDL

This paper briefly presents architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values (-1;0;+1;+2) or (-2;-1; 0;+1) is proposed leading to a multiplier design with less complex partial products implementation. To implement some proposed preencoded NR4SD multipliers, including the coefficients memory to prove that they are more area and power efficient than the conventional Modified Booth scheme. By this proposed design the performance increases upto25% by decreasing 30%area and power consumption. By this critical path delay also decreases with decrease in area and power consumption.